SSDs typically include flash-based memory media, such as NAND media, a flash memory controller, and a memory buffer, such as DRAM and/or SRAM. The NAND media can be a single-level cell (SLC) media storing one bit of memory data per cell, or the NAND media can be multibit NAND media, such as multi-level cell (MLC) media and triple-level cell (TLC) media storing two bits of memory data per cell and three bits of memory data per cell, respectively. The need for higher capacity SSDs capable of storing hundreds to thousands of terabytes (TBs) of data or more drives the increasing development and adoption of multibit NAND media. To achieve this level of storage capacity, NAND media with increasing storage density is required. Development of the next-generation of multibit NAND media, quad-level cell (QLC) media, capable of storing four bits of memory data per cell is ongoing, and it is foreseeable that flash-based memory media capable of storing an even greater number of bits of memory data per cell will be developed in the future.
The use of increasingly dense multibit NAND media presents a number of issues. For example, it is well known that TLC NAND media is more prone to read errors than MLC NAND media, which in turn is more prone to read errors than SLC NAND media. So when a host sends data to be written to the SSD, the data will be first buffered in the DRAM and/or SRAM to undergo error correction parity encoding before it can be written to the TLC NAND media. Error correction parity encoding of the data slows the performance of the SSD because it is very time consuming.
Because TLC NAND media is more prone to read errors, it also has higher error correction requirements. For example, a low-density parity check (LDPC) error correction scheme may be able to support up to 120 bit-flips per one kilobyte (KB) of data read from the TLC NAND media, whereas a Bose-Chaudhuri-Hocquenghem (BCH) error correction scheme may be able to support up to 120 bit-flips per 2 KB of data read from the TLC NAND media. In the case of BCH error correcting code (ECC) with TLC NAND media, the SSD's ECC engine would likely not be able to properly correct data read from the TLC NAND media on a fairly regular basis (i.e. the BCH ECC capability is exceeded), and a more robust ECC mechanism is required, such as Quadruple Swing-By Code (QSBC) developed by Toshiba which has ten times the error correction capability of typical BCH ECC. The tradeoff, however, is that more robust ECC mechanisms such as QSBC also take longer to perform (measured in milliseconds (ms) as compared to less robust mechanisms such as BCH which are measured in microseconds (μs)).
Finally, due to the storage density and programming requirements of TLC NAND media, writing data to and reading data from TLC NAND media also takes longer to perform as compared to SLC and MLC NAND media. Thus, typical SSDs using TLC NAND media will have substantially reduced input/output operations per second (IOPs) as compared to SSDs using SLC NAND media. Further, for next-generation multibit NAND media, such as QLC NAND media and beyond, a further reduction in performance will be likely given the probable proportional increase in read errors necessitating more frequent use of robust ECC mechanisms and proportional decrease in IOPs due to increasing storage density.
There is, therefore, an unmet demand for SSDs addressing the performance and host-read error issues with multibit NAND media.